Instead of wiggling a sideband pin in PCI. In PCI-X the device just does what it already knows how to do: write to memory.

1. Pre-defined Address Range

   • The system reserves a special “interrupt address range” in memory.
   • Writing to this region doesn’t store data in RAM — instead, it’s intercepted by the CPU/APIC as an interrupt message.

2. Unique Interrupt Vector

   • Along with the write, the device includes a data payload (the interrupt vector).
   • This vector is unique to that device (or even to a specific queue in the device).

3. Delivery to CPUs

   • The system maps that vector to a particular CPU (or multiple CPUs).
   • The CPU instantly knows which device/queue raised the interrupt and jumps directly to the correct interrupt service routine (ISR).

Benefits of MSI

• ✅ No shared pins → avoids interrupt conflicts.
• ✅ Lower latency → CPU doesn’t need to poll devices to find the source.
• ✅ Scalable → devices can request multiple interrupt vectors (e.g., a multi-queue NIC can assign one vector per queue).
• ✅ No extra wires → interrupts use standard memory transactions, simplifying board design.
• ✅ Better SMP support → interrupts can be delivered to specific CPUs in multi-core/multi-CPU systems.